Memory devices such as MRAM have been continuously scaled down in size to accommodate complex device requirements and low power consumption demands. However, the smaller form factor has also increased the complexity of memory device fabrication. Critical dimensions (CD) of memory cells are smaller compared to normal back-end-of-line (BEOL) process variations. A particular area of challenge faced by manufacturers due to such limitations is extending a pillar contact formed within a memory device to a desired height.
Typically, pillar contacts are difficult to form accurately and consistently into a desired shape or surface type due to limited process margin. For example, etching of a pillar contact, e.g., a memory array or an electrode, may cause sidewall erosion, resulting in tapering of the pillar contact tip instead of formation of a square tip (flat, uniform contact surface). Still further, multiple pillar contacts of a memory device may vary in uniformity due to the height of an applied planarization material overtaking the height of some of the pillar contacts, erosion of the pillar contact shape/contact surface type during chemical-mechanical polishing (CMP), etc. In certain instances, the device manufacturer may apply an additional/reverse mask dielectric material (e.g., a carbon-doped oxide) atop the contacts as a means of reshaping them or extending them to achieve a desired height. However, this requires additional topographic etching to remove the applied mask and further increases the fabrication cost.
A need therefore exists for methodology for cost effectively forming pillar contact extensions within a memory device with minimal fabrication process variation and without direct interlayer dielectric (ILD) CMP, and the resulting device.